That only brings DRAM into alignment with flash and magnetic storage, so it's not really a negative. Everything in your computer is converging on semiconductor with bounded probabilistic state + math.

It's always been that way, just how many nines of reliability we're talking about. E.g. at Google scale, bitflips in memory from cosmic rays and general noise happy every day. Everything has checksums on it.

May you please ELI5 why DDR5 is 'fragile' as you put it?

Was its design pushing material sciences such that the theory worked, but practical implementation required the 'crutch' of ECC?

basically. pushing the timing and sizes makes it likely that some of your bits will fail to be built correctly. rather than dropping the speed and sizes to get reliability, you just throw an extra chip on to give you redundancy.

Take a look at the spec. The speeds are so high that they use some modem channel characterization features on the memory bus.

Linus was right about ECC being needed, with higher capacities and speeds and reduced feature size it's becoming a must.