The applications are the same, but an FPGA allows extremely narrow optimization. Got something that doesn't parallelize all that well, but can be pipelined, or benefits from a wide datapath? Design that. Got something that parallelizes well and only needs a tiny datapath? Make it a 1000 wide vector machine. It needs difficult control flow? No problem, we're flexible as we're not a GPU, etc.
The optimization needs to beat out the inefficiency of the FPGA compared to an ASIC though (not to speak of development time). But sometimes, you can do just that.
The optimization needs to beat out the inefficiency of the FPGA compared to an ASIC though (not to speak of development time). But sometimes, you can do just that.