Oh yeah, I completely forgot to mention proximity. 10x 100nF caps might be superior to 1x 1uF simply because the latter can only be close to 1 pin whereas the first can be close to 10 power supply pins.
Looking at the left diagram under the "Decoupling capacitor placement" headline here:
... it is very obvious that the cap being 1cm away will already cause much worse degradation than what going from 100nF to 1uF could ever improve.
Many modern chips have multiple power input pins. Using smaller caps close to all of them will do much better than fewer bigger better caps, but with more distance.
I like this article a lot, but it doesn't hammer home the fullest, easiest statement of this kind of lazy-best-effort decoupling: pick the smallest package you are willing to deal with, then buy the biggest value of capacitor you are willing to pay for in that package. Loop area really does rule all, and if you don't know that, you're going to have a hard time of it.
The article also doesn't do a particularly good job of making the argument against relying on the "notch" (seen here at 25–40MHz), which is that the notch moves. It moves around with just about any change in... anything... so you can either pay the heavy price to genuinely control it (it can be actually worthwhile to drop a notch on things in certain analog applications; think knocking out a DAC clock frequency in a reconstruction filter) or you can ignore that the notch exists. Usually that's the easier option!
>Oh yeah, I completely forgot to mention proximity. 10x 100nF caps might be superior to 1x 1uF simply because the latter can only be close to 1 pin whereas the first can be close to 10 power supply pins.
That's the point of the article, though. 1uF caps are now available in package sizes smaller than 100nF caps were when the rule of thumb originated. You can get a 16V rates uF cap in 0201 nowadays, so proximity really isn't a problem.
I second the general rule of thumb: stacking decoupling capacitors is extremely rarely needed nowadays. Pick your size, put the largest capacitor you can get in that size (or, if you're paranoid and think the manufacturers might be pushing things, go one size smaller) as close to the chip as you can, and maybe assess if you need some bulk capacitance as well, but more likely you are liable to wind up with too much capacitance.
> assess if you need some bulk capacitance as well, but more likely you are liable to wind up with too much capacitance
Remember also that most bulk capacitor types bring in some ESR, and the associated damping can really help a PDN. If you're too lazy to simulate, at least leave a footprint for a tantalum or aluminum capacitor!
Looking at the left diagram under the "Decoupling capacitor placement" headline here:
https://jmw.name/projects/exploring-pdns/
... it is very obvious that the cap being 1cm away will already cause much worse degradation than what going from 100nF to 1uF could ever improve.
Many modern chips have multiple power input pins. Using smaller caps close to all of them will do much better than fewer bigger better caps, but with more distance.