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> In fact the hypervisor extension was explicitly designed to be relatively efficient to implement in software emulation.

Fair point, I stand corrected on that one. Should have checked more thoroughly before posting.

> It even says so at the URL you failed to include

That site doesn't render right on my mobile, which I was on at the time, so couldn't read the contents.

> "[...] by running the hypervisor in S-mode [...]"

That doesn't sound very efficient if all you got is an M-mode-only chip though.

In any event, you also have extensions like Ztso[2], which even the spec says to just let the binary crash in event of non-presence, or Zam[3] which you technically could emulate but surely would be dog slow.

[1]: https://five-embeddev.com/riscv-priv-isa-manual/Priv-v1.12/p...

[2]: https://five-embeddev.com/riscv-user-isa-manual/Priv-v1.12/z...

[3]: https://five-embeddev.com/riscv-user-isa-manual/Priv-v1.12/z...

[4}: https://www.riscfive.com/2022/12/07/sifive-intelligence-fami...




> That doesn't sound very efficient if all you got is an M-mode-only chip though.

There is approximately a light-year of space between an M-mode-only chip and anything where you'd consider running a hypervisor.

Suggesting that you want a hypervisor is implicitly saying that you already have S and U modes, virtual memory, page tables, MMU etc.

Otherwise you're at much the same point as those news stories about how someone is running RISC-V Linux on an AVR or Pi Pico (original) or vim macros, by writing a RISC-V emulator on one of those.


Hey, OP wanted RISC-V binaries to run anywhere, not me...




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