> I really wish RISC-V had been designed in such a way that every RISC-V core must run every RISC-V binary.
Obviously impossible, given that commercially-available RISC-V chips start from 2 KB RAM, 16 registers, and 48 MHz.
> wouldn't mean every core must implement every possible instruction - instead, unimplemented features would be emulated
And that is exactly what RVA23 is.
Every instruction must work. Nothing requires them to be fast. Missing instructions or capabilities (e.g. misaligned load/store) are handled in M-mode software, transparent to both the User program and the operating system.
> Then, the fragmentation problem turns from a "it won't work" problem into a "it might not be quite as fast" problem - and for general users, that effectively means everything is 100% compatible.
Obviously impossible, given that commercially-available RISC-V chips start from 2 KB RAM, 16 registers, and 48 MHz.
> wouldn't mean every core must implement every possible instruction - instead, unimplemented features would be emulated
And that is exactly what RVA23 is.
Every instruction must work. Nothing requires them to be fast. Missing instructions or capabilities (e.g. misaligned load/store) are handled in M-mode software, transparent to both the User program and the operating system.
> Then, the fragmentation problem turns from a "it won't work" problem into a "it might not be quite as fast" problem - and for general users, that effectively means everything is 100% compatible.
That is exactly the situation with RVA23.