no, the mask must be made within the tight rules of the proprietary (and very secret) PDK of the TSMC Fab for that node. Just getting it certified that it fits the rules will cost millions.
It's probably more of a node thing than a fab thing. You would have a much easier time getting the fab to do random stuff for you on a legacy node compared to a leading edge node.
Leading edge nodes are basically black magic and are right on the edge of working vs producing broken chips.
You as a customer would never want to be in a position where you are solely responsible for yields.
There are only a few Fabs with nodes smaller than 28nm. Yes, all fabs are like that, with exception of a few experimental tiny labs at research institutes or universities.
Maybe in reality it is somewhere in-between, where TSMC says: here is a set of standard cells that we tested; you can use them but if you modify anything then it's at your own risk.
Maybe in therory, yes. In practise the fab will never allow you to do anything at your own risk because it might contaminate or break their $170 million machine. If you offer a few billion extra to cover that risk, your cheaper off building your own fab instead.
It takes years just to figure out how to use the machines to produce actual working chips. They're the most specialized, intricate, expensive machines in the world. They're operated in enormous clean rooms that only allow for 1 half-micron sized particle per cubic foot. No fab is going to run them without exactly following the procedures they have spent billions developing and testing. They are also going to avoid potential delays as much as possible because these machines have to be running for as much of their useful life as possible to recoup the vast expense. The level of risk-averseness is insane, but warranted.
If you haven't watched this video, I highly recommend it: Indistinguishable From Magic: Manufacturing Modern Computer Chipshttps://www.youtube.com/watch?v=NGFhc8R_uO4 It's a little outdated now, but very comprehensive and gives you an idea of how totally nuts the chip business is.
Think of it less like moving transistors around and more like moving small groups of atoms around (also, you can get single transistor cells for analog and power designs). The processes required to place the rough groups of atoms in roughly specific places involves extreme amounts of energy relative to the size of what you are working with, which is supplied in a combination of chemical, radiation, and thermal forms. As a result, predicting what additional effects attempting to form specific micro-shapes might have is nontrivial. They extensively simulate and then carefully test all of their approved cells on an ongoing basis. Deviating from this could cause unknown issues, including damage, but doing the necessary work to prequalify your custom cells would be prohibitively expensive for most applications.
Going outside of the PDK rules you risk contamination because a chip machine is a high speed ultra-accurate automated mechanical and chemical laboratory. It sprays extremely corrosive acids and vaporizes metals. Going a nanometer outside of the rules would send droplet or flakes of chemicals flying around at high speed.
I'm very skeptical of this too. I don't see a mechanism where moving transistors could break the machine. Although I wonder if you could blow up the die testing machine by making a chip that was one big charge pump :-)
It's not obvious what "moving" means in this thread but no foundry would ever let you make a design the grossly violates the design rule checks (DRC). It's hard to imagine how something risking damage of anything would get through all the many, many, checks, but wasting time and money is definitely possible and to be avoided.
As an aside, few analog layouts will use the "line of diffusion" style that's common in the standard cells. And in analog one can find more exotic transistor patterns, like waffle [1], that aren't used in digital. Many things are possible, but it has to pass DRC.
Skeptical here as well, no one is proposing a serious mechanism for damage like "you left gate oxide uncovered by silicide so it contaminates the CMP machine" or whatever.
What I can imagine, is that the foundry only tests their magic OPC algorithm with DRC clean inputs. If your mask isn't DRC clean, who knows what's coming out the other side.
