When do you anticipate supporting UVM based testbenches? Verilator is definitely very fast, and SV assertions and coverage are powerful, however the lack of native UVM will require existing ASIC teams to develop new stimulus and checkers that they already have developed.
UVM support is a high priority for us, and our current infrastructure should make it basically drop-in once it's ready. Drop me an email if you are interested (email in bio), we will be sure to let you know when it's ready! :)
