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A binary rate-monotonic scheduler. It was in the Ada realtime executive for an avionics box (there was no OS). It executed tasks at 5 rates, each half as fast as the previous one. It was dead simple, something like (pseudocode)

    counter = 1

    do highest priority stuff
    case counter
        when 1, 3, 5, 7, 9, 11, 13, 15
            do high priority stuff
        when 2, 6, 10, 14
            do medium priority stuff
        when 4, 12
            do low priority stuff
        when 8
            do lowest priority stuff (1st half)
        when 16
            do lowest priority stuff (2nd half)
    end

    counter++
    if counter > 16
        counter = 1
    end
This was called on a timer interrupt.

I was like "what the heck does this do?" followed by "that sure reminds me of binary trees" and finally "whoa! cool!"




This is quite close to how it would be done in hardware. I find that after writing Verilog/VHDL you tend to write code like this.




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