The statement is about relative timings, to be clear, and you agreed with that.
I'm not trying to be clever here to win an argument, I really just think that good relative timing is implied by "accuracy", and good wall-clock timing is not--that's "performance". It makes sense to me that these terms are separate, so I can say something like "I have a cycle-accurate emulator that runs at 25x realtime".
For stuff like game systems, you generally don't need a ton of wall-clock accuracy anyway. You're going to be plugged into some kind of LCD panel, and you just need to make sure that it gets fed with the correct data every 16 ms or whatever the correct update rate is. The fact that your input controller isn't getting probed at the exact right time relative to the screen update is kind of a non-issue.
Yeah, we agree on relative timings, and I guess I'm okay with using "accuracy" without qualification for that, i.e. what the machine observes. It wasn't clear to me that "timing" meant cycle-accuracy, so I guess we do agree after all.
As for how much wall-clock accuracy you need... Eh, as said, it depends on how much of a preservationist you are. If you plan to actually generate an NTSC or PAL signal on a low level (including actually performing the quadrature amplitude modulation), it can well become relevant, and phase noise affects color.
Otherwise maybe not, though again I'm not surprised if some standard Linux on some RPi actually shows visible glitches from time to time. Irrelevant for most users, but then again most users may also just want to play the game on a rudimentary emulator, or even a more modern version of the game. This is all either for fun or for preservation, after all.
If you do need (video signal) or want (anal retentiveness) high wall-clock accuracy, an FPGA then also has the advantage that whatever ARM core or whatever you have next to it can implement UI and control in whatever is most convenient, on any non-RT run of the mill OS, without any risk to negatively affect the rock-solid, cycle-locked emulation in the FPGA. On an overall weaker overall SoC at lower frequency, even.
