The issue for me is that ARM is also really old now. I mean, just look at the ISA Apple has to use to run their MacOS on it: it's littered with NEON extensions and more cruft than you can shake a stick at. Simply put, Apple's implementation of ARM is decidedly CISC. On top of this, I'm still dumbfounded by the fact that they didn't go for a chiplet design where ARM could truly shine: if Apple had went the chiplet route, the M1 could have had a much higher IO ceiling and might have a shot at addressing more than 16 gigs of RAM.
Apple has a much bigger issue, though. ARM doesn't scale: it's a fundamental conceit of the architecture, one that a lot of people are probably willing to take on a laptop that will mostly be used for Twitter and YouTube. This presents issues for the rest of the market though, and it will be fascinating to see how Apple retains their pro userbase while missing out on the high-performance hardware sector entirely.
I think x86 is pretty terrible too, if it's any consolation, but really it's the only option you've got as a programmer in the 21st century. I hopped on the Raspberry Pi bandwagon when I was still in middle school, I grew up rooting for the little guy here. Looking out on the future landscape of computer hardware though, I really only see RISC-V. ARM is an improvement on x86, but I don't think it's profound enough to make people care. RISC-V, on the other hand, blows both of them out of the water. On consumer hardware, it's able to accelerate pretty much any workload while sipping a few mW. On professional hardware, you can strap a few hundred of those cores together and they'll work together to create highly complex pipelines for data processing. On server hardware, it will probably move like gangbusters. Even assuming that cloud providers pocket half the improvements, a 5x price/performance increase will have the business sector racing to support it.
So yeah, it is a pretty complex situation. Apple did a cool thing with the M1, but they have a long ways to go if they want to dethrone x86 in it's entirety.
As far as I understand it, “CISC” doesn’t mean “has a lot of instructions”, it means the individual instructions are themselves complex/composable/expressing more than one hardware operation. For instance, on x86 you can write an instruction like ‘ADD [rax + 0x1234 + 8*rbx], rcx’ that performs a multi-step address calculation with two registers, reads from memory, adds a third register, and writes the result back to memory — and you can stick on prefix bytes to do even more things. ARM doesn’t have anything like that; it is a strict load/store architecture where every instruction is fixed-width with a regular format and either accesses memory or performs a computation on registers.
Stuff like hardware primitives for AES/SHA, or the FJCVTZS “JavaScript instruction” don’t make a processor CISC just because they’re specialized. They all encode trivial, single-cycle hardware operations that would otherwise be difficult to express in software (even though they may be a bit more specialized than something like “add”, they’re not any more complex). x86 is CISC because the instruction encoding is more complicated, specifying
many hardware operations with one software instruction.
I’m not exactly sure whar all the “cruft” is in ARM that you’re referring to. The M1 only implements AArch64, which is less than 10 years old and is a completely new architecture that is not backwards-compatible with 32-bit ARM (it has been described as being closer to MIPS than to arm32). NEON doesn’t strike me as a good example of cruft because SIMD provides substantial performance gains for math-heavy programs, and in any case 10 years of cruft is much better than 45.
I’m curious as to why RISC-V is different or better? I don’t know much about RISC-V — but looking at the Wikipedia article, it just looks like a generic RISC similar to MIPS or AArch64 (and it’s a couple years older than AArch64 as well). Is there some sort of drastic design difference I’m missing?
The only advantage I’ve heard put forward for RISC-V on single threaded applications is the existence of compressed instructions - which could reduce cache misses albeit at the expense of a slightly more complex decoder. I’m a bit sceptical as to whether this is material though as cache sizes increase.
Of course the flexibility of the RISC-V model allows approaches such as that being pursued by Esperanto [1] with lots and lots of simpler cores.
ARM had THUMB, which definitely improved performance back in the GameBoy days — but they dropped that with AArch64, so presumably they decided it wasn’t beneficial anymore.
> On top of this, I'm still dumbfounded by the fact that they didn't go for a chiplet design where ARM could truly shine: if Apple had went the chiplet route, the M1 could have had a much higher IO ceiling and might have a shot at addressing more than 16 gigs of RAM.
Remember that M1 is just a mobile SoC that work for iPad/MacBook Air. It's exceptionally great so people tend to confuse M1 is targeted higher end. 16GB max is fine for a mobile SoC in 2021. I can't wait M1X.
If you don't think arm can scale any further, why do you think x86 can? They could easily double all the specs in the "M2" and slap two+ of them into a mac pro.
Apple has a much bigger issue, though. ARM doesn't scale: it's a fundamental conceit of the architecture, one that a lot of people are probably willing to take on a laptop that will mostly be used for Twitter and YouTube. This presents issues for the rest of the market though, and it will be fascinating to see how Apple retains their pro userbase while missing out on the high-performance hardware sector entirely.
I think x86 is pretty terrible too, if it's any consolation, but really it's the only option you've got as a programmer in the 21st century. I hopped on the Raspberry Pi bandwagon when I was still in middle school, I grew up rooting for the little guy here. Looking out on the future landscape of computer hardware though, I really only see RISC-V. ARM is an improvement on x86, but I don't think it's profound enough to make people care. RISC-V, on the other hand, blows both of them out of the water. On consumer hardware, it's able to accelerate pretty much any workload while sipping a few mW. On professional hardware, you can strap a few hundred of those cores together and they'll work together to create highly complex pipelines for data processing. On server hardware, it will probably move like gangbusters. Even assuming that cloud providers pocket half the improvements, a 5x price/performance increase will have the business sector racing to support it.
So yeah, it is a pretty complex situation. Apple did a cool thing with the M1, but they have a long ways to go if they want to dethrone x86 in it's entirety.