"Once the Yosys gHDL integration stabilize, CXXRTL will be the only open source simulator with mixed Verilog/VHDL language support!"

Folks, this is huge! There isn't a single commercial ASIC/SoC project that doesn't have a mix of Verilog and VHDL.

Yosys, Yosys Open SYnthesis Suite, is a Free Verilog Synthesis Suite.