There is the fin pitch, the gate pitch, the metal pitch, and (related) the track height (which is a design density number). Fin pitch shrinks a little, gate pitch a little, track lots (Intel used to use 9-12, moving to 6). There is also space between device boundaries, which also can be shrunk.

The 5nm is the gate half pitch, which is no longer a sufficient description. All else being equal, simple shrink would shrink everything, and that gate half pitch would be useful. That hasn't been true for 15 years.

Density comes at the cost of performance and yield, so you balance different aspects to get the right combination. Or _a_ right combination for your design.