1. Heat dissipation is now ~n x m times worse where n is your transistor layer count. And where m is the increased thermal resistance*

2. Power delivery is now ~n times worse where n is your transistor layer count. *

3. Connections between chips are very slow, power hungry and expensive. Fabrication of "monolithic" 3D is temperature wise painful and usually results in crummier transistors.

With that being said, innovative 3D integration methods in specific applications can help a lot. Shameless plug: we at Vathys do this for deep learning chips.

* to a first order of approximation

The heat can be tackled in part by pumping water through holes in the CPU. I believe it was IBM that came up with this. Can't tell if it's feasible or not.

Yes but microfluidics limits how thin each die can be.

What about stacked heat vias ?

What are those? Do you mean something like thermal "dummy" vias?

yeah, something imprinted in all layers so you could evacuate heat

I was thinking by either creating a temperature differential on a copper conductor to chill the cube from within or that the motherboard/walls would provide cooling from the pin side.

They do use some 3D techniques inside dies. Tri-gate transistors and 3DICs, for insurance

Yes well FinFETs and other non planar transistors are very different from what's being discussed here. Interestingly, FinFETs actually do suffer from a bit of a self heating effect although this usually isn't a problem for AC operation.

That still means multiple silicon dies, which we have known how to do for a while (see: Intel Core 2 Quad from 2006, and more recently AMD Epyc).

Having more dies lets you dissipate more heat, but then it's kinda hard to build low-latency / high-bandwidth interconnects between the dies. Inter-die buses go over a PCB or interposer, which impose higher parasitic capacitance and make it difficult/expensive to run wide interfaces. That's why techniques like "dark silicon" allocation are important - it allows us to get more perf in a single die.

less surface area per transistor makes the heat problem worse. they are already a little bit 3d though.

If I understand correctly, neither heat dissipation nor existing manufacturing techniques are amenable to this approach. Also modern CPUs do have more than a dozen layers IIRC.

I think op is talking about 6 flat normal chips as the sides. This would allow for cooling stuff inside the cube. Maybe having only 5 of the sides as chips would make it even easier to have a heat sink. The center of the cube could be copper or something.

You can't cool from the inside of that cube without having some way of transporting the heat out of it.

All you'd end up doing is heating that inside up to the temperature of the dies and after that there would be no more cooling effect (and this would happen in a few seconds after starting the whole thing up). You could do an 'inverse' of this by cooling the dies from the outside and having the interconnects in the space in between. This would still require a lot of cooling and there would be an issue with connecting the resulting assembly to the underlying PCB.

I think woah means that the top would be open. So instead of a cube it'd be an open box. A heat sink (or arrangement of peltier coolers attached to a fan and heat sink, or whatever) would fit down into the box and be in contact with the five core-containing sides.

What if you used electronic cooling to chill a copper thermal conductor?

Electronic cooling? Do you mean Peltier elements? They have a 'hot' and a 'cold' side, and their capacity is handily outstripped by any modern CPU. If that worked we would be using Peltier coolers to make quiet PCs today, after all, that problem is only 1/5th as complex.

Another problem is that companies (though not necessarily users) love thinner and thinner phones and laptops, and a cubic CPU wouldn't fit in such a device.

> Why don't they start making CPUs 3 Dimensional like a cube with 6 "processors" each with multiple cores as its "sides" with the pins on the opposite sides of the cube wall.

Not directly an answer to this specific question, but a (somewhat) colleague who writes his PhD thesis about 3-dimensional chip design made a popular scientific lecture about this topic. As I understood it, the central problem is that it is very hard to produce chips with multiple (lots of) layers (where you want to have interconnects inbetween). In particular producing the interconnects between the layers is really hard if they can lie "everywhere" instead of only at the border. There exist multiple ideas how this might be done (e.g. drill holes with high-precission lasers into the substrate and try to fill them with something conductive), but none of them as of today "really works" (at least if we are talking about chips with somewhat more than 4 layers and interconnects everywhere inbetween).

Fun fact: the through silicon via was invented by William Shockley himself

For heat dissipation you want the most surface area per volume (because you can only transfer heat away in the surface area). The optimal arrangement for that would be a huge, flat, one atom thick surface.

Another goal we have is low latency (and high clock rate, which is depenend on low latency), which suggests putting everything in a qube or even a shere. So we compromise somewhere in the middle with a square with a few layers.

"For heat dissipation you want the most surface area per volume (because you can only transfer heat away in the surface area). The optimal arrangement for that would be a huge, flat, one atom thick surface."

Made me think of this:

https://en.wikipedia.org/wiki/Menger_sponge

Say we have roughly 300 sq mm, that's about 17.32 mm square, which is 8.24e+7 silicon atoms (0.21 nm) across.

Then we have a surface area of roughly 1.36e+16 atoms - the area x 2.

If we make a fractal sponge down to the limit of single atoms, then that's about 16.5 cycles of removing cubes from a 17.32 mm cube. Let's ignore the difficulty of doing it half a time. According to the formulas from wikipedia, the result has a volume of about 0.7% of the original, with 2.4e28 "sides" of atoms exposed.

So the third dimension gets you about 1.8 million times the surface area. I suppose this isn't nearly as good as 4e10 flat sheets with 1 atom separation between each, but you could argue it's more practical because everything is connected...

Re "I suppose this isn't nearly as good as 4e10 flat sheets with 1 atom separation between each" - I guess it should be better, actually, now that I happened to notice 10+16 < 28. I got confused about whether my reference point was the basic cube or the flat sheet.

I think a dimpled fabrication would be best... with whatever amounts to heat sinks on both sides.

Such a "side cube" configuration would probably lead to longer wires than is useful.

Just the reverse. As volume increases, the relative amount of surface area decreases.