So, anyone willing to risk an FPGA implementation?

There is some plausible verilog code on that page and schematics. It looks like Brad got a core design running in simulation - no evidence of synthesis or IO (yet?).

Tempting - amongst 1e6 other things.

Same here.

So much to do, so little free time...

How wonderful. However can you get more than a glimpse of the real thing without one of those extrardinary keyboards? ( see for instance the later http://www.asl.dsl.pipex.com/symbolics/photos/IO/index.html )

I find the lack of cursor keys will be disturbing to the uninitiated.

Last time I checked, it would be expensive, perhaps prohibitively, to build a small batch of them.